View AD8333ACPZ-WP_3769834.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dc to 50 mhz, dual i/q demodulator and phase shifter ad8333 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2010 analog devices, inc. all rights reserved. features dual integrated i/q demodulator 16 phase select options on each output (22.5 per step) quadrature demodulation accuracy phase accuracy: 0.1 amplitude balance: 0.05 db bandwidth 4 lo: 100 khz to 200 mhz rf: dc to 50 mhz baseband: determined by external filtering output dynamic range: 159 db/hz lo drive > 0 dbm (50 ); 4 lo > 1 mhz supply: 5 v power consumption: 190 mw/channel (380 mw total) power-down applications medical imaging (cw ultrasound beamforming) phased array systems (radar and adaptive antennas) communication receivers functional block diagram 90 0 90 0 i1po/ i1no q1po/ q1no q2po/ q2no i2po/ i2no ph1x ph2x 4lop 4lon 4 ad8333 rf1p rf1n rf2p rf2n 05543-001 enbl rset figure 1. general description the ad8333 is a dual-phase shifter and i/q demodulator that enables coherent summing and phase alignment of multiple analog data channels. it is the first solid-state device suitable for beamformer circuits, such as those used in high performance medical ultrasound equipment featuring cw doppler. the rf inputs interface directly with the outputs of the dual-channel, low noise preamplifiers included in the ad8332 . a divide-by-4 circuit generates the internal 0 and 90 phases of the local oscillator (lo) that drive the mixers of a pair of matched i/q demodulators. the ad8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment. the ad8333 features an asynchronous reset pin. when used in arrays, the reset pin sets all the lo dividers in the same state. sixteen discrete phase rotations in 22.5 increments can be selected independently for each channel. for example, if channel 1 is used as a reference and the rf signal applied to channel 2 has an i/q phase lead of 45, channel 2 can be phase aligned with channel 1 by choosing the correct code. phase shift is defined by the output of one channel relative to another. for example, if the code of channel 1 is adjusted to 0000 and that of channel 2 is adjusted to 0001 and the same signal is applied to both rf inputs, the output of channel 2 leads that of channel 1 by 22.5. the i and q outputs are provided as currents to facilitate summation. the summed current outputs are converted to voltages by a high dynamic range, current-to-voltage (i-v) converter, such as the ad8021 , configured as a transimpedance amplifier. the resultant signal is then applied to a high resolution adc, such as the ad7665 (16 bit/570 ksps). the two i/q demodulators can be used independently in other nonbeamforming applications. in that case, a transimpedance amplifier is needed for each of the i and q outputs, four in total for the dual i/q demodulator. the dynamic range is 159 db/hz at the i and q outputs, but the following transimpedance amplifier is an important element in maintaining the overall dynamic range, and attention needs to be paid to optimal component selection and design. the ad8333 is available in a 32-lead lfcsp (5 mm 5 mm) package for the industrial temperature range of ?40c to +85c.
ad8333 rev. d | page 2 of 32 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? esd caution.................................................................................. 5 ? pin configuration and function descriptions............................. 6 ? equivalent input circuits ................................................................ 7 ? typical performance characteristics ............................................. 8 ? test circuits..................................................................................... 14 ? theory of operation ...................................................................... 17 ? quadrature generation ............................................................. 17 ? i/q demodulator and phase shifter ........................................ 17 ? dynamic range and noise........................................................ 18 ? summation of multiple channels (analog beamforming) .. 19 ? phase compensation and analog beamforming................... 19 ? channel summing ..................................................................... 20 ? dynamic range inflation .......................................................... 22 ? disabling the current mirror and decreasing noise............ 22 ? applications information .............................................................. 24 ? logic inputs and interfaces....................................................... 24 ? reset input .................................................................................. 24 ? connecting to the lna of the ad8331/ad8332/ad8334/ad8335 vgas............................ 24 ? interfacing to other amplifiers ............................................... 25 ? lo input ...................................................................................... 25 ? evaluation board ............................................................................ 26 ? features and options ................................................................. 26 ? measurement setup.................................................................... 27 ? evaluation board schematic and artwork.................................. 28 ? board layout............................................................................... 30 ? outline dimensions ....................................................................... 32 ? ordering guide .......................................................................... 32 ? revision history 9/10rev. c to rev. d change to i2no, q2no, q1no, and i1no pin description, table 3 ................................................................................................ 6 changes to figure 62, features and options section, table 5, phase nibble section, and enable and reset switches section.............................................................................................. 26 changes to reset input section, measurement setup section, and figure 63................................................................................... 27 changes to figure 64...................................................................... 28 changes to figure 65...................................................................... 29 changes to figure 66 through figure 70.................................... 30 deleted ordering information section ....................................... 37 deleted table 7; renumbered sequentially ................................ 37 9/08rev. b to rev. c changes to figure 1.......................................................................... 1 changes to general description section ...................................... 1 change to table 2 ............................................................................. 5 changes to figure 4 and figure 6................................................... 7 change to figure 18 ......................................................................... 9 changes to dynamic range and noise section ......................... 18 changes to connecting to the lna of the ad8331/ad8332/ ad8334/ad8335 vgas section .................................................. 24 added interfacing to other amplifiers heading ....................... 25 changes to figure 61...................................................................... 25 incorporated ad8333-evalz data sheet.................................. 26 changes to evaluation board section.......................................... 26 changes to features and options section................................... 26 changes to table 5.......................................................................... 26 replaced the phase bits section with the phase nibble section.............................................................................................. 26 deleted table 2...................................................................................3 changes to lna input impedance section ................................ 26 changes to current summing section........................................ 26 changes to measurement setup section ..................................... 27 moved figure 63; changes to figure 63...................................... 27 changes to figure 64...................................................................... 28 moved figure 70 ............................................................................. 30 changes to table 7.......................................................................... 31 deleted figure 62; renumbered sequentially ............................ 26 updated outline dimensions....................................................... 32 changes to ordering guide .......................................................... 32 5/07rev. a to rev. b changes to features and figure 1 ...................................................1 changes to table 1.............................................................................3 changes to figure 41 to figure 43................................................ 14 changes to figure 44 to figure 47................................................ 15 changes to figure 48 to figure 51................................................ 16 changes to figure 55...................................................................... 20 changes to evaluation board section.......................................... 25 changes to ordering guide .......................................................... 27 5/06rev. 0 to rev. a changes to figure 62...................................................................... 26 10/05revision 0: initial version
ad8333 rev. d | page 3 of 32 specifications v s = 5 v, t a = 25c, f 4lo = 20 mhz, f rf = 5.01 mhz, f bb = 10 khz, p lo 0 dbm, single-ended, sine wave; per channel performance, dbm (50 ), unless otherwise noted (see figure 41 ). table 1. parameter conditions min typ max unit operating conditions lo frequency range 4 internal lo at pin 4lop and pin 4lon square wave 0.01 200 mhz sine wave, see figure 22 2 200 mhz rf frequency range mixing dc 50 mhz baseband bandwidth limited by external filtering dc 50 mhz lo input level see figure 22 0 13 dbm v supply (v s ) 4.5 5 6 v temperature range ?40 +85 c demodulator performance rf differential input impedance 6.7||6.5 k||pf lo differential input capacitance 0.6 pf transconductance demodulated i out /v in , each i or q output after low-pass filtering measured from rf inputs, all phases 2.17 ms dynamic range ip1db, input-referred noise (dbm) 159 db/hz maximum rf input swing differential; inputs biased at 2.5 v; pin rfxp and pin rfxn 2.8 v p-p peak output current (no filtering) 0 phase shift 4.7 ma 45 phase shift 6.6 ma input p1db reference = 50 14.5 dbm reference = 1 v rms 1.5 dbv third-order intermodulation (im3) f rf1 = 5.010 mhz, f rf2 = 5.015 mhz, f lo = 5.023 mhz equal input levels baseband tones: ?7 dbm at 8 khz and 13 khz ?75 dbc unequal input levels baseband tones: ?1 dbm at 8 khz and ?31 dbm at 13 khz ?77 dbc third-order input intercept (ip3) f rf1 = 5.010 mhz, f rf2 = 5.015 mhz, f lo = 5.023 mhz 30 dbm lo leakage measured at rf inputs, wors t phase, measured into 50 (limited by measurement) ad8333 rev. d | page 4 of 32 parameter conditions min typ max unit logic interfaces logic level high pin phxx, pin rset, and pin enbl 1.7 5 v logic level low pin phxx, pin rset, and pin enbl 0 1.3 v bias current pin phxx and pin enbl logic high 10 40 90 a logic low ?30 ?7 +10 a pin rset logic high 50 120 180 a logic low ?70 ?20 0 a input resistance pin phxx and pin enbl 60 k pin rset 20 k reset hold time reset is asynchronous; clock di sabled when rset goes high until 300 ns after rset goes low; see figure 58 300 ns minimum reset pulse width 300 ns reset response time see figure 35 300 ns phase shifting response time see figure 38 5 s enable response time see figure 34 300 ns power supply pin vpos and pin vneg supply voltage 4.5 5 6 v quiescent current, all phase bits = 0 at 25c pin vpos 38 44 51 ma pin vneg ?24 ?20 ?16 ma over temperature ?40c < t a < 85c pin vpos, all phase bits = 0 40 54 ma pin vneg ?24 ?19 ma quiescent power per channel, all phase bits = 0 170 mw per channel, any 0 or 1 combination of phase bits 190 mw disable current all channels disabled pin vpos 1.0 1.25 1.5 ma pin vneg ?300 ?200 ?100 a psrr pin vpos to i/q outputs (measured at ad8021 output) ?81 db pin vneg to i/q outputs (measured at ad8021 output) ?75 db
ad8333 rev. d | page 5 of 32 absolute maximum ratings table 2. parameter rating voltages supply voltage, v s 6 v rf pins input v s , gnd lo inputs v s , gnd code select inputs voltage v s , gnd thermal data 1 ja 41.0c/w jb 23.6c/w jc 4.4c/w jt 0.4c/w jb 22.4c/w maximum junction temperature 150c maximum power dissipation (exposed pad soldered to pc board) 1.5 w operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 4-layer jedec board no airflow (exposed pad soldered to pcb).
ad8333 rev. d | page 6 of 32 pin configuration and fu nction descriptions pin 1 indicator 1 ph12 2 ph13 3 comm 4 4lop 5 4lon 6 lodc 7 ph23 8 ph22 24 i1po 23 q1po 22 q1no 21 vneg 20 comm 19 q2no 18 q2po 17 i2po 9 ph21 10 ph20 11 vpos 12 rf2p 13 rf2n 14 vpos 15 rset 16 i2no 32 ph11 31 ph1 0 30 vpo s 29 rf1p 28 rf1n 27 vpo s 26 enbl 25 i1no ad8333 top view (not to scale) 05543-002 notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the paddle be soldered to the ground plane. figure 2. 32-lead lfcsp pin configuration table 3. pin function descriptions pin no. nemonic description 1, 2, 7, 8 ph12, ph13, ph23, ph22 quadrant select lsb, msb. binary code. these logic in puts select the quadrant: 0 to 90, 90 to 180, 180 to 270, 270 to 360 (see table 4 ). logic threshold is at about 1.5 v and therefore can be driven by 3 v cmos logic (see figure 3 ). 3, 20 comm ground. these two pins are internally tied together. 4, 5 4lop, 4lon lo inputs. no internal bias; therefore, these pins n eed to be biased by external circuitry. for optimum performance, these inputs should be driven differentially with a signal level that is not less than what is shown in figure 22 . bias current is only ?3 a. single-ended driv e is also possible if the inputs are biased correctly (see figure 4 ). 6 lodc decoupling pin for lo. a 0.1 f capacitor should be connected between this pin and ground (see figure 5 ). 9, 10, 31, 32 ph21, ph20, ph10, ph11 phase select lsb, msb. binary code. these logic inputs select the phase for a given quadrant: 0, 22.5, 45, 67.5 (see table 4 ). logic threshold is at about 1.5 v and ther efore can be driven by 3 v cmos logic (see figure 3 ). 11, 14, 27, 30 vpos positive supply. these pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 f and 100 pf capacitor between the vpos pins and ground. becaus e the vpos pins are internally connected, one set of supply decoupling components for all four pins should be sufficient. 12, 13, 28, 29 rf2p, rf2n, rf1n, rf1p rf inputs. these pins are biased internally; however, it is recommended that they be biased by dc coupling to the output pins of the ad8332 lna. the optimum common-mode voltage for maximum symmetrical input differential swing is 2.5 v if 5 v supplies are used (see figure 6 ). 15 rset reset for divide-by-4 in lo interface. logic threshold is at about 1.5 v and therefore can be driven by 3 v cmos logic (see figure 3 ). 16, 19, 22, 25 i2no, q2no, q1no, i1no negative i/q outputs. not connected for typical applications. 17, 18, 23, 24 i2po, q2po, q1po, i1po positive i/q outputs. these outputs provide a bidirectional current that can be converted back to a voltage via a transimpedance amplifier. multiple outputs can be su mmed together by connecting them together. the bias voltage should be set to 0 v or less by the transimpedance amplifier (see figure 7 ). 21 vneg negative supply. this pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 f and 100 pf capacitor between the pin and ground. 26 enbl chip enable. logic threshold is at about 1.5 v and therefore can be driven by 3 v cmos logic (see figure 3 ).
ad8333 rev. d | page 7 of 32 equivalent input circuits logic interface vpos comm phxx enbl rset 05543-003 figure 3. logic inputs 4lop 4lon comm v pos 05543-004 figure 4. local os cillator inputs lodc vpos comm 05543-005 figure 5. local oscillator decoupling pin comm v pos rfxn rfxp 05543-006 figure 6. rf inputs comm vneg ixno qxno ixpo qxpo 05543-007 figure 7. output drivers
ad8333 rev. d | page 8 of 32 typical performance characteristics v s = 5 v, t a = 25c, f 4lo = 20 mhz, f lo = 5 mhz, f rf = 5.01 mhz, f bb = 10 khz, p lo 0 dbm (50 ); single-ended sine wave; per channel performance, differential voltages, dbm (50 ), phase select code = 0000, unless otherwise noted (see figure 41). 1.5 ?1.5 ?2.0 2.0 real phase (normalized) imaginary phase (normalized) 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 code 0000 code 0100 code 1100 code 1000 code 0001 code 0010 code 0011 05543-008 f = 1mhz q i figure 8. normalized vector plot of phase, channel 2 with respect to channel 1; channel 1 is fixed at 0, channel 2 stepped 22.5/step, all codes displayed 360 0 0000 1111 code (binary) phase (degrees) 315 270 225 180 135 90 45 0010 0100 0110 1000 1010 1100 1110 05543-009 1mhz 5mhz figure 9. phase of channel 2 with respect to channel 1 vs. code at 1 mhz and 5 mhz 1.0 ?1.0 0000 1111 code (binary) amplitude error (db) 0.5 0 ?0.5 ?1.0 1.0 0.5 0 ?0.5 0010 0100 0110 1000 1010 1100 1110 f = 5mhz f = 1mhz 05543-010 figure 10. amplitude error of channel 2 with respect to channel 1 vs. code at 1 mhz and 5 mhz 2 ?2 0000 1111 code (binary) phase error (degrees) 1 0 ?1 ?2 2 1 0 ?1 0010 0100 0110 1000 1010 1100 1110 f = 5mhz f = 1mhz 05543-011 figure 11. phase error of channel 2 with respect to channel 1 vs. code at 1 mhz and 5 mhz 05543-012 20s 500mv figure 12. i or q output of channe l 2 with respect to channel 1, first quadrant shown 7 3 1m 50m rf frequency (hz) gain (db) 10m 6 5 4 05543-013 channel 1, i output shown code 0000 code 0001 code 0010 code 0011 figure 13. conversion gain vs. rf frequency, first quadrant, baseband frequency = 10 khz
ad8333 rev. d | page 9 of 32 2.0 ?2.0 1m 100m rf frequency (hz) quadrature phase error (degrees) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 10m 05543-014 figure 14. representative range of quadrature phase errors vs. rf frequency, channel 1 or channel 2, all codes 2.0 ?2.0 100 100k baseband frequency (hz) quadrature phase error (degrees) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 1k 10k 05543-015 figure 15. representative range of quadrature phase error vs. baseband frequency, channel 1 and channel 2 (see figure 43 ) 0.5 ?0.5 1m 50m rf frequency (hz) i/q amplitude imbalance (db) 10m 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 05543-016 figure 16. representative range of i/q amplitude imbalance vs. rf frequency, channel 1 or channel 2, all codes 0.5 ?0.5 100 100k baseband frequency (hz) i/q amplitude imbalance (db) 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 1k 10k 05543-017 figure 17. representative range of i/q amplitude imbalance vs. baseband frequency, channel 1 and channel 2 (see figure 43 ) 2.0 ?2.0 1m 50m rf frequency (hz) amplitude match (db) 10m 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 05543-018 f bb = 10khz i2/i1 displayed code 0000 ?40c +25c +85c code 0001 ?40c +25c +85c code 0010 ?40c +25c +85c code 0011 ?40c +25c +85c figure 18. typical i2xo/i1xo or q2xo/q1xo amplitude match vs. rf frequency, first quadrant, at three temperatures 8 ?4 1m 05543-043 rf frequency (hz) phase error (degrees) 10m 50m 6 4 2 0 ?2 f bb = 10khz i2/i1 displayed code 0000 ?40c +25c +85c code 0001 ?40c +25c +85c code 0010 ?40c +25c +85c code 0011 ?40c +25c +85c figure 19. i2xo/i1xo or q2xo/q1x o phase error vs. rf frequency, baseband frequency = 10 khz, at three temperatures
ad8333 rev. d | page 10 of 32 2.8 2.0 1m 50m rf frequency (hz) transconductance (ms) 10m 2.7 2.6 2.5 2.4 2.3 2.2 2.1 05543-020 code 0000 code 0001 code 0010 code 0011 channel 1, i output shown transconductance = [(v bb /787 ? )v rf ] figure 20. transconductance vs. rf frequency, first quadrant 10 ?80 ?20 0 power (dbm) gain (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?15 ?10 ?5 05543-021 f = 5mhz gain = v bb /v rf code 0000 code 0001 code 0010 code 0011 figure 21. conversion gain vs . lo level, first quadrant 5 ?40 100k 100m rf frequency (hz) minimum lo level (dbm) 1m 10m 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 all codes region of useable lo levels 05543-022 figure 22. minimum lo level vs. rf frequency, single-ended, sine wave lo drive to pin 4lop or pin 4lon 10 ?30 0 5.0 common-mode voltage (v) gain (db) 05543-019 5 0 ?5 ?10 ?15 ?20 ?25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 gain = v bb /v rf +85c +25c ?40c figure 23. lo common-mode range at three temperatures 20 0 1m 50m rf frequency (hz) ip1db (dbm) 18 16 14 12 10 8 6 4 2 05543-023 10m figure 24. ip1db vs. rf frequency, baseband frequency = 10 khz, first quadrant (see figure 42 ) 10m 0 ?90 1m 50m rf frequency (hz) im3 (dbc) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 both channels ?7dbm 3 8 13 18 im3 products lo = 5.023mhz rf1 = 5.015mhz rf2 = 5.010mhz 05543-024 figure 25. representative range of im3 vs. rf frequency, first quadrant (see figure 49 )
ad8333 rev. d | page 11 of 32 10m 40 0 1m 50m rf frequency (hz) oip3 (dbm) 35 30 25 20 15 10 5 both channels 05543-025 figure 26. representative range of oip3 vs. rf frequency, first quadrant (see figure 49 ) 35 0 1k 100k baseband frequency (hz) oip3 (dbm) 10k 30 25 20 15 10 5 05543-026 channel 1 rf channel 2 rf figure 27. oip3 vs. ba seband frequency (see figure 48 ) 0 ?80 1m 50m rf frequency (hz) lo leakage (dbm) 10m ?10 ?20 ?30 ?40 ?50 ?60 ?70 lo level = 0dbm 05543-027 i1 i2 q1 q2 figure 28. lo leakage vs. rf frequency at baseband outputs 0 ?140 1m 50m rf frequency (hz) lo leakage (dbm) 10m 05543-028 lo level = 0dbm ?20 ?40 ?60 ?80 ?100 ?120 rf1p rf2p rf1n rf2n figure 29. lo leakage vs. rf frequency at rf inputs 16 ?142.9 0 1m 50m rf frequency (hz) noise (nv/ hz) noise (dbm) 10m 14 ?144.1 12 ?145.4 10 ?147.0 8 ?148.9 6 ?151.4 4 ?154.9 2 ?161.0 05543-029 i1 q1 figure 30. input-referred noise vs. rf frequency 20 0 1m 05543-064 rf frequency (hz) noise figure (db) 10m 50m 18 16 14 12 10 8 6 4 2 figure 31. noise figure vs. rf frequency with ad8332 lna
ad8333 rev. d | page 12 of 32 172 152 1m 50m rf frequency (hz) dynamic range (db) 10m 170 168 166 164 162 160 158 156 154 05543-030 i1 q1 i1 + i2 q1 + q2 figure 32. dynamic range vs. rf fr equency, ip1db minus noise level, single channel and two channels summed 6 ?10 ?3.0 1.0 05543-044 voltage (v) gain (db) 4 2 0 ?2 ?4 ?6 ?8 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 gain = v bb /v rf code 0000 code 0010 figure 33. output compliance range (ixpo, qxpo) (see figure 50 ) 200ns 2v 500mv 05543-045 figure 34. enable responsetop: enable signal, bottom: output signal (see figure 44 ) 200ns 2v 500mv 05543-046 figure 35. reset responsetop: signal at rset pin, bottom: output signal (see figure 45 ) 40s 5v 1v 1v 05543-047 figure 36. phase switching responsechannel 2 leads channel 1 by 45, top: input to ph21, select code = 0010; bottom (red): reference channel 1 i out ; bottom (gray): channel 2 i out phase shifted 45, channel 1 reference phase select code = 0000 40s 5v 1v 1v 05543-048 figure 37. phase shifting responsechannel 2 leads channel 1 by 90, top: input to ph21, select code = 0100; bottom (red): reference channel 1 i out ; bottom (gray): channel 2 i out phase shifted 90, channel 1 reference phase code = 0000
ad8333 rev. d | page 13 of 32 5v 1v 1v 40s 05543-049 figure 38. phase shifting responsechannel 2 leads channel 1 by 180, top: input to ph23 select code = 1000; bottom (red): reference channel 1 i out ; bottom (gray): channel 2 i out phase shifted 180, channel 1 reference phase code = 0000 0 ?90 100k 50m 05543-050 frequency (hz) psrr (db) 1m 10m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 vneg vpos figure 39. psrr vs. frequency (see figure 51 ) 60 0 ?50 90 05543-051 temperature (c) quiescent supply current (ma) 50 40 30 20 10 ?30 ?10 10 30 50 70 vneg vpos figure 40. quiescent supply current vs. temperature
ad8333 rev. d | page 14 of 32 test circuits oscilloscope lpf 50? signal generator 120nh fb 0.1f 0.1f ad8332 lna 20? 20? signal generator 50? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop 787 ? 787 ? 2.2nf 2.2nf 05543-032 figure 41. default test circuit oscilloscope lpf 50? signal generator 120nh fb 0.1f 0.1f ad8332 lna 20? 20? signal generator 50? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop 100 ? 100 ? 10nf 10nf 05543-033 figure 42. p1db test circuit oscilloscope lpf 50 ? signal generator 120nh fb 1f 1f ad8332 lna 20 ? 20? signal generator 50 ? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop 787 ? 787 ? 05543-034 figure 43. phase and amplit ude vs. baseband frequency
ad8333 rev. d | page 15 of 32 oscilloscope lpf 50 ? signal generator 120nh fb 1f 1f ad8332 lna 20? 20 ? signal generator 50? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop signal generator 50? enbl 787? 787? 05543-035 figure 44. enable response oscilloscope lpf 50 ? signal generator 120nh fb 1f 1f ad8332 lna 20? 20 ? signal generator 50? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop signal generator 50? rst 787? 787? 05543-036 figure 45. reset response oscilloscope lpf 50? signal generator 120nh fb 0.1f 0.1f a d8332 lna 20? 20 ? signal generator 50? ad8333 rfxp ixxo rfxn qxxo 4lop 50 ? 50? 05543-037 figure 46. rf input range spectrum analyzer signal generator 50? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop 6.98k ? 6.98k ? 270pf 270pf 0.1f 05543-052 figure 47. noise test circuit
ad8333 rev. d | page 16 of 32 120nh fb 0.1f 0.1f ad8332 lna 20 ? 20? signal generator 50? signal generator 50 ? signal generator 50 ? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop 787? 787? 100pf 100pf 05543-053 combiner ?6db spectrum analyzer figure 48. oip3 vs. baseband frequency 120nh fb 0.1f 0.1f ad8332 lna 20 ? 20? signal generator 50? signal generator 50 ? signal generator 50 ? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop 787? 787? 2.2nf 2.2nf 05543-054 combiner ?6db spectrum analyzer figure 49. oip3 and im3 vs. rf frequency oscilloscope lpf 50? signal generator 120nh fb 0.1f 0.1f ad8332 lna 20? 20? signal generator 50 ? ad8333 rfxp ixxo rfxn qxxo ad8021 a d8021 4lop 787 ? 787 ? 2.2nf 2.2nf 05543-055 figure 50. output compliance range network analyzer lpf 50? signal generator 120nh fb 0.1f 0.1f a d8332 lna 20? 20 ? signal generator 50? ad8333 rfxp ixxo rfxn qxxo 4lop 05543-056 figure 51. psrr test circuit
ad8333 rev. d | page 17 of 32 theory of operation the ad8333 is a dual i/q demodulator with a programmable phase shifter for each channel. the primary applications are phased array beamforming in medical ultrasound, phased array radar, and smart antennae for mobile communications. the ad8333 can also be used in applications that require two well- matched i/q demodulators. for optimum performance, the 4lox inputs are driven differ- entially but can also be driven in a single-ended fashion. a good choice for a drive is an lvds device. the common-mode range on each pin is approximately 0.2 v to 3.8 v with nominal 5 v supplies. the minimum lo level is frequency dependent (see figure 22 ). for optimum noise performance, it is important to ensure that the lo source has very low phase noise (jitter) and adequate input level to ensure stable mixer-core switching. the gain through the divider determines the lo signal level vs. rf frequency. the ad8333 can be operated to very low frequencies at the lo inputs if a square wave is used to drive the lo. figure 52 shows the block diagram and pinout of the ad8333. three analog and nine quasilogic level inputs are required. two rf inputs accept signals from the rf sources and a local oscillator (applied to the differential input pins marked 4lox) common to both channels constitute the analog inputs. four logic inputs per channel define one of 16 delay states/360 (or 22.5 /step), selectable with phx0 to phx3. the reset input is used to synchronize ad8333s used in arrays. beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. a reset pin (rset) is provided to synchronize the 4lox divider circuits when ad8333s are used in arrays. the rset pin resets the counters to a known state after power is applied to multiple ad8333s. a logic input must be provided to the rset pin when using more than one ad8333. see the reset input section for more details. 90 0 90 0 - - - 4 - buf bias ad8333 32 ph11 9 ph21 31 ph10 10 ph20 30 vpos 11 vpos 29 rf1p 12 rf2p 28 rf1n 13 rf2n 27 vpos 14 vpos 26 enbl 15 rset 25 i1no 16 i2no 24 i1po 1 ph12 23 q1po 2 ph13 22 q1no 3 c omm 20 comm 5 4lon 21 vneg 4 4lop 19 q2no 6 lodc 18 q2po 7 ph23 17 i2po 8 ph22 channel 1 - sel logic channel 2 - sel logic 05543-057 i/q demodulator and phase shifter the i/q demodulators consist of double-balanced gilbert cell mixers. the rf input signals are converted into currents by transconductance stages that have a maximum differential input signal capability of 2.8 v p-p. these currents are then presented to the mixers, which convert them to baseband: rf ? lo and rf + lo. the signals are phase shifted according to the code applied to pin phx0 to pin phx3 (see table 4 ). the phase shift function is an integral part of the overall circuit (patent pending). the phase shift listed in column 1 of table 4 is defined as being between the baseband i or q channel outputs. as an example, for a common signal applied to the rf inputs of an ad8333, the baseband outputs are in phase for matching phase codes. however, if the phase code for channel 1 is 0000 and that of channel 2 is 0001, channel 2 leads channel 1 by 22.5. figure 52. block diagram and pinout each of the current formatted i and q outputs sum together for beamforming applications. multiple channels are summed and converted to a voltage using a transimpedance amplifier. if desired, channels can also be used individually. following the phase shift circuitry, the differential current signal is converted from differential to single ended via a current mirror. an external transimpedance amplifier is needed to convert the i and q outputs to voltages. quadrature generation the internal 0 and 90 lo phases are digitally generated by a divide-by-4 logic circuit. the divider is dc-coupled and inherently broadband; the maximum lo frequency is limited only by its switching speed. the duty cycle of the quadrature lo signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4lox inputs. furthermore, the divider is implemented such that the 4lox signals reclock the final flip- flops that generate the internal lo signals and thereby minimizes noise introduced by the divide circuitry.
ad8333 rev. d | page 18 of 32 table 4. phase nibble select codes shift phx3 phx2 phx1 phx0 0 0 0 0 0 22.5 0 0 0 1 45 0 0 1 0 67.5 0 0 1 1 90 0 1 0 0 112.5 0 1 0 1 135 0 1 1 0 157.5 0 1 1 1 180 1 0 0 0 202.5 1 0 0 1 225 1 0 1 0 247.5 1 0 1 1 270 1 1 0 0 292.5 1 1 0 1 315 1 1 1 0 337.5 1 1 1 1 dynamic range and noise figure 53 is an interconnection block diagram of the ad8333. for optimum system noise performance, the rf input signal is provided by a very low noise amplifier, such as the lna of an ad8332 or the preamplifier of an ad8335. in beamformer applications, the i and q outputs of a number of receiver channels are summed (for example, the two channels illustrated in figure 53 ). the dynamic range of the system increases by the factor 10 log 10 (n), where n is the number of channels (assuming random uncorrelated noise). the noise in the two-channel example of figure 53 is increased by 3 db while the signal doubles (6 db), yielding an aggregate snr improvement of (6 db ? 3 db) = 3 db. judicious selection of the rf amplifier ensures the least degradation in dynamic range. the input-referred spectral voltage noise density (e n ) of the ad8333 is nominally 9 nv/ hz to 10 nv/ hz. for the noise of the ad8333 to degrade the system noise figure (nf) by 1 db, the combined noise of the source and the lna should be about twice that of the ad8333, or 18 nv/ hz. if the noise of the circuitry before the ad8333 is <18 nv/ hz, the system nf degrades more than 1 db. for example, if the noise contribution of the lna and source is equal to the ad8333, or 9 nv/ hz, the degradation is 3 db. if the circuit noise preceding the ad8333 is 1.3 as large as that of the ad8333 (or about 11.7 nv/ hz), the degradation is 2 db. for a circuit noise of 1.45 that of the ad8333 (13.1 nv/ hz), the degradation is 1.5 db. to determine the input-referred noise, it is important to know the active low-pass filter (lpf) values r filt and c filt , shown in figure 53 . typical filter values (for example, those used on the evaluation board) are 787 and 2.2 nf and implement a 90 khz single-pole lpf. if the rf and lo are offset by 10 khz, the demod- ulated signal is 10 khz and is passed by the lpf. the single-channel mixing gain from the rf input to the ad8021 output (for example, i, q) is approximately 1.7 4.7 db. this together with the 9 nv/ hz ad8333 noise results in about 15.3 nv/ hz at the ad8021 output. because the ad8021 , including the 787 feedback resistor, contributes another 4.4 nv/ hz, the total output-referred noise is about 16 nv/ hz. this value can be adjusted by increasing the filter resistor while maintaining the corner frequency, thereby increasing the gain. the factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the i-to-v converter, in this instance the ad8021. - - - - i1 q1 q2 i2 2 2 2 2 2 2 2 2 4 4 2 2 0 90 90 0 ad8333 4 clock generator transmitter transducer transmitter transducer t/r sw r fb r fb ad8332 lna or ad8335 preamp ad8332 lna or ad8335 preamp ch1 rf ch2 rf channel 1 phase select channel 2 phase select t/r sw ad8021 ad8021 ad7665 or ad7686 c filt c filt r filt r filt i data q data adc 16-bit 570ksps adc 16-bit 570ksps 05543-038 * * *up to eight channels per ad8021 q i figure 53. interconnection block diagram
ad8333 rev. d | page 19 of 32 summation of multiple channels (analog beamforming) beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source but received at different times by a multielement ultrasound transducer. beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. the primary application for the ad8333 is in analog beamforming circuits for ultrasound. phase compensation and analog beamforming modern ultrasound machines used for medical applications employ a 2 n binary array of receivers for beamforming, with typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. when used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor n, where n is the number of channels), while the noise is increased by the square root of the number of channels. this technique enhances the signal-to-noise performance of the machine. the critical elements in a beamformer design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. in traditional analog beamformers incorporating doppler, a v-to-i converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. the system operates at the receive frequency (rf) through the delay line, and then the signal is down- converted by a very large dynamic range i/q demodulator. the resultant i and q signals are filtered and sampled by two high resolution adcs. the sampled signals are processed to extract the relevant doppler information. alternatively, the rf signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal and then combining all channels. the ad8333 provides the means to implement this architecture. the downconversion is done by an i/q demodulator on each channel, and the summed current output is the same as in the delay line approach. the subsequent filters after the i-to-v conversion and the adcs are similar. the ad8333 integrates the phase shifter, frequency conversion, and i/q demodulation into a single package and directly yields the baseband signal. to illustrate this, figure 54 is a simplified diagram showing two channels. the ultrasound wave (usw) is received by two transducer elements, te1 and te2, in an ultrasound probe and generates the e1 and e2 signals. in this example, the phase at te1 leads the phase at te2 by 45. e1 e2 19db lna 19db lna s1 s2 45 usw at te1 leads usw at te2 by 45 transduce r elements te1 and te2 convert usw to electrical signals ad8332 es1 leads es2 by 45 ad8333 phase bit settings ch 1 ref (no phase lead) ch 2 phase lead 45 s1 and s2 are now in phase summed output s1 + s2 05543-063 figure 54. simplified example of the ad8333 phase shifter in a real application, the phase difference depends on the element spacing, (wavelength), speed of sound, angle of incidence, and other factors. the es1 and es2 signals are amplified 19 db by the low noise amplifiers in the ad8332. for optimum signal-to-noise performance, the output of the lna is applied directly to the input of the ad8333. to sum the es1 and es2 signals, es2 is shifted 45 relative to es1 by setting the phase code in channel 2 to 0010. the phase-aligned current signals at the output of the ad8333 are summed in an i-to-v con- verter to provide the combined output signal with a theoretical improvement in dynamic range of 3 db for the sum of two channels.
ad8333 rev. d | page 20 of 32 channel summing in a beamformer using the ad8333, the bipolar currents at the i and q outputs are summed directly. figure 55 illustrates 16 summed channels (for clarity, these channels are shown as current sources) as an example of an active current summing circuit using the ad8333. this figure also illustrates ad8021s as first-order current summing circuits and ad797 s as low noise second-order summing circuits. beginning with the op amps, there are a few important considerations in the circuit shown in figure 55 . the op amps selected for the first-order summing amplifiers must have good frequency response over the full operating frequency range of the ad8333s and be able to source the current required at the ad8333 i and q outputs. the total current of each ad8333 is 6.6 ma for the multiples of the 45 phase settings (code 0010, code 0110, code 1010, and code 1110) and is divided nearly equally between the baseband frequencies (including a dc component) and the second harmonic of the local oscillator frequency. the desired cw signal tends to be much less (<40 db) than the unwanted interfering signals. when determining the large signal requirements of the first-order summing amplifiers and low-pass filters, the very small cw signal can be ignored. the number of channels that can be summed is limited by the output drive current capacity of the op amp selected: 60 ma to 70 ma for a linear output current for 5 v and 12 v, respectively, for the ad8021 . because the ad8021 implements an active lpf together with r1x and c1x, it must absorb the worst-case current provided by the ad8333, for example, 6.6 ma. therefore, the maximum number of channels that the ad8021 can sum is 10 for 12 v or eight for 5 v supplies. in practical applications, cw channels are used in powers of two, thus the maximum number per ad8021 is eight. another consideration for the op amp selected as an i-to-v converter is the compliance voltage of the ad8333 i and q outputs. the maximum compliance voltage is 0.5 v, and a dc bias must be provided at these pins. the ad8021 active lpf satisfies these requirements; it keeps the outputs at 0 v via the virtual ground at the op amp inverting input while providing any needed dc bias current. 3 + 2 3 + 2 3 ad797 + 2 a first-order summing amplifiers c1a 18nf lpf1a 88khz r1a 100? ? ? b ? 0.1f 0.1f ad8021 ?5v +5v c2a 1f c3a 5.6nf r2a 698 ? r3a 698 ? lpf2a 81khz hpf1a 100hz +2.8v baseband signal c1b 18nf r1b 100? 0.1f 0.1f ad8021 +5v ?5v c2b 1f c3b 5.6nf r2b 698 ? r3b 698 ? r4 +10v ?10v 0.1f 0.1f second-order summing amplifier 05543-058 (same as above) eight ad8333 i or q outputs, 6.6ma peak each (if the phase setting is 45) 3.3ma at dc + 3.3ma at 2 lo figure 55. a 16-channel beamformer
ad8333 rev. d | page 21 of 32 as previously noted, a typical cw signal has a large dc and very low frequency component compared with its desired low cw doppler baseband frequency, and another unwanted component at the 2 lo. the dc component flows through the gain resistors r1x, and the 2 lo flows through the capacitors c1x. the smaller desired cw doppler baseband signal is in the frequency range of 1 khz to 50 khz. because the output current of the ad8333 contains the baseband frequency, a dc component, and the 2 lo frequency voltages, the desired small amplitude baseband signal must be extracted after a series of filters. these are shown in figure 55 as lpfna, hpfna, and gain stages. before establishing the value of c lpf1 , the resistor r lpf1 is selected based on the peak operating current and the linear range of the op amp. because the peak current for each ad8333 is 6.6 ma and there are eight channels to be summed, the total peak current required is 52.8 ma. approximately half of this current is dc, and the other half is at a frequency of 2 lo. therefore, about 26.4 ma flows through the resistor, and the remaining 26.4 ma flows through the capacitor. r1 was selected as 100 and, after filtering, generates a peak dc and very low frequency voltage of 2.64 v at the ad8021 output. for power supplies of 5 v, 100 is a good choice for r1. however, because the cw signal needs to be amplified as much as possible and the noise degradation of the signal path minimized, the value of r1 should be as large as possible. a larger supply helps in this regard, and the only factor limiting the largest supply voltage is the required power. for a 10 v supply on the ad8021 , r1 can be increased to 301 to realize the same headroom as with a 5 v supply. if a higher value of r1 is used, c1 must be adjusted accordingly (in this example, 1/3 the value of the original value) to maintain the desired lpf roll-off. the principal advantage of a higher supply is greater dynamic range, and the trade-off is power consumption. the user must weigh the trade-offs associated with the supply voltage, r1, c1, and the following circuitry. a suggested design sequence is as follows: 1. select a low noise, high speed op amp. the spectral density noise (e n ) should be <2 nv/hz, and the 3 db bandwidth should be 3 the expected maximum 2 lo frequency. 2. divide the maximum linear output current by 6.6 ma to determine the maximum number of ad8333 channels that can be summed. 3. select the largest value of r1 that permits the output voltage swing within the power supply rails. 4. calculate the value of c1 to implement the lpf corner that allows the cw doppler signal to pass with maximum attenuation of the 2 lo signal. the filter lpf1a establishes the upper frequency limit of the baseband frequency and is selected well below the 2 lo frequency, typically 100 khz or less (for example, 88 khz in figure 55 ). a useful equation for calculating c1 is lpf1 r1f c1 2 1 = (1) as previously mentioned, the ad8333 output current contains a dc current component. this dc component is converted to a large dc voltage by the ad8021 lpf. capacitor c2 filters this dc component and, with r2 + r3, establishes a high-pass filter with a low frequency cutoff of about 100 hz. capacitor c3 is much smaller than c2 and, consequently, can be neglected. c2 can be calculated by hpf1 fr3r2 c2 )( 2 1 + = (2) to achieve maximum attenuation of the 2 lo frequency, a second low-pass filter, lpf2, is established using the parallel combination of r2 and r3, and c3. its ?3 db frequency is 3)||(2 1 2 cr3r2 f lpf = (3) in the example shown in figure 55 , f lpf2 = 81 khz. finally, the feedback resistor of the ad797 must be calculated. this is a function of the input current (number of channels) and the supply voltage. the second-order summing amplifier requires a very low noise op amp, such as the ad797 , with 0.9 nv/hz, because the amplifier gain is determined by feedback resistor r4 divided by the parallel combination of the lpf2a resistors seen looking back toward the ad8021 s. referring to figure 55 , the ad797 in-band (100 hz to 88 khz) gain is expressed as [] )(||) ( r2br2br3ar2a r4 + + (4) the ad797 noise gain can increase to unacceptable levels because the denominator of the gain equation is the parallel resistance of all the r2 + r3 resistors in the ad8021 outputs. for example, for a 64-channel beamformer, the resistance seen looking back toward the ad8021 s is about 1.4 k/8 = 175 . for this reason, the value of (r2x + r3x) should be as large as possible to minimize the noise gain of the ad797 . (note that this is the case for the ad8021 stages because they look back into the high impedance current sources of the ad8333s.) due to these considerations, it is advantageous to increase the gain of the ad8021 s as much as possible because the value of (r2x + r3x) can be increased proportionally. resistors (r2x + r3x) convert the cw voltages to currents that are summed at the inverting inputs of the ad797 op amp, and then amplified and converted to voltages by r4.
ad8333 rev. d | page 22 of 32 the value of r4 needs to be chosen iteratively as follows: 1. determine the number of ad8021 first-order summing amplifiers. in figure 55 , there are two; for a 32-channel beamformer, there would be four, and for a 64-channel beamformer, there would be eight. 2. determine the output noise from the ad8021 s. a first- order calculation can be based on a value of ad8333 output current noise of about 20 pa/hz. for the values in figure 55 , this results in about 6 nv/hz for eight channels after the ad8021 s. adding the noise of the ad8021 and the 100 feedback resistor results in about 6.5 nv/hz total noise after the ad8021 lpf in the cw doppler band. 3. determine the noise of the circuitry after the ad797 and determine the desired signal level. 4. determine the voltage and current noise of the second- order summing amplifiers. 5. choose a value for (r2x + r3x) and for r4. determine the resulting output noise after the ad797 for one channel, and then multiply this value by the square root of the number of summed ad8021 s. next, check ad797 output noise (both current and voltage noise). ideally, the sum of the noise of the resistors and the ad797 should be less than a factor-of-3 than the noise due to the ad8021 outputs. 6. check the following stages output noise against the calculated noise from the combiner circuit and ad8333s. ideally, the noise from the following stage should be less than 1/3 of the calculated noise. 7. if the combined noise is too large, experiment with increasing/decreasing values for (r2x + r3x) and r4. to simplify, the user can also simulate or build a combiner circuit for optimum performance. it should be noted that the ~20 pa/hz output from the ad8333 is for the ad8333 with shorted rf inputs. in an actual system, the current noise output from the ad8333 is most likely dominated by the noise from the ad8332 lna and the noise from the source and other circuitry before the lna. this helps ease the design of the combiner. the preceding procedures for determining the optimum values for the combiner are based on the noise floor of the ad8333 only. as an example, for a 32-channel beamformer using four low- pass filters, as shown in figure 55 , (r2x + r3x) = 1.4 k and r4 = 6.19 k. the theoretical noise increase of n is degraded by only about 1 db. dynamic range inflation although all 64 channels can theoretically be summed together at a single amplifier, it is important to realize that the dynamic range of the summed output increases by 10 log 10 (n) if all channels have uncorrelated noise, where n is the number of channels to be summed. the summed signal level increases by a factor of n, whereas the noise increases only as n. in the case of 64 channels, this is an increase in dynamic range of 18 db. note that the ad8333 dynamic range is already about 160 db/hz; the summed dynamic range is 178 db/hz (equivalent to about 29.5 bits/hz). in a 50 khz noise bandwidth, this is 131 db (21.7 bits). disabling the current mirror and decreasing noise the noise contribution of the ad8333 can potentially be reduced if the current mirrors that convert the internal differential signals to single-ended signals are bypassed (see figure 56 ). current mirrors interface to the ad8021 i-v converters shown in figure 53 , and output capacitors across the positive and negative outputs provide low-pass filtering. the ad8021 s force the ad8333 output voltage to 0 v and then process the bipolar output current; however, the internal current mirrors introduce a significant amount of noise. this noise can be reduced if the mirrors are disabled and the outputs are externally biased. the mirrors are disabled by connecting vneg to ground and providing external bias networks, as shown in figure 56 . the larger the drop across the resistors, the less noise they contribute to the output; however, the voltage on the i and q output nodes cannot exceed 0.5 v. voltages exceeding approximately 0.7 v turn on the pnp devices and forward bias the esd protection diodes. inductors provide an alternative to resistors, enabling reduced static power by eliminating the power dissipation in the bias resistors. vneg 1 1 note that pin vneg and pin comm are connected together. comm ixno qxno ixpo qxpo i-v i-v 05543-039 other channels figure 56. bypassing the internal current mirrors with inductors, the main limitation might be low frequency operation, as is the case in cw doppler in ultrasound where the frequency range of interest goes from a few hundred hertz to about 30 khz. in addition, it is still important to provide enough gain through the i-to-v circuitry to ensure that the bias resistor and i-to-v converter noise do not contribute significantly to the noise from the ad8333 outputs. another approach is to provide a single external current mirror that combines all channels; it is also possible to implement a high-pass filter with this circuit to help with offset and low frequency reduction.
ad8333 rev. d | page 23 of 32 the main disadvantage of the external bias approach is that two i-v amplifiers are needed because of the differential output (see figure 56 ). for beamforming applications, the outputs are still summed, but there is twice the number of lines. only two bias resistors are needed for all outputs that are connected together. the resistors are scaled by dividing the value of a single output bias resistor through n, the number of channels connected in parallel. the bias current depends on the phase selected: for phase 0, it is about 2.5 ma per side, whereas in the case of 45, it is about 3.5 ma per side. the bias resistors should be chosen based on the larger bias current value of 3.5 ma and the chosen vneg. vneg should be at least ?5 v and can be larger for additional noise reduction. excessive noise or distortion at high signal levels degrades the dynamic range of the signal. transmitter leakage and echoes from slow moving tissue generate the largest signal amplitudes in ultrasound cw doppler mode and are largest near dc and at low frequencies. a high-pass filter introduced immediately following the ad8333 reduces the dynamic range. this is shown by the two coupling capacitors after the external bias resistors in figure 56 . users have to determine what is acceptable for a particular application. care must be taken in designing the external circuitry to avoid introducing noise via the external bias and low frequency reduction circuitry.
ad8333 rev. d | page 24 of 32 applications information the ad8333 is the key component of a phase-shifter system that aligns time-skewed information contained in rf signals. combined with a variable gain amplifier (vga) and low noise amplifier (lna), the ad8333 forms a complete analog receiver for a high performance ultrasound system. figure 57 is a block diagram of a complete receiver using the ad8333, ad8331, ad8332 , and ad8334. processor i1 q1 16-bit adc 16-bit adc processor i2 q2 processor hs adc processor hs adc ad8332 lna1 lna2 ad8333 from t ransduce r t/r switch from t ransduce r t/r switch 05543-059 figure 57. block diagramultrasound receiver using the ad8333 and ad8332 lna as a major element of an ultrasound system, it is important to consider the many i/o options of the ad8333 that are necessary to perform its intended function. figure 61 shows the basic connections. logic inputs and interfaces the logic inputs of the ad8333 are all bipolar-level sensitive inputs. they are not edge triggered, nor are they to be confused with classic ttl or other logic family input topologies. the voltage threshold for these inputs is vpos 0.3, so for a 5 v supply the threshold is 1.5 v, with a hysteresis of 0.2 v. although the inputs are not of themselves logic inputs, any 5 v logic family can drive them. reset input the rset pin is used to synchronize the lo dividers in ad8333 arrays. because they are driven by the same internal lo, the two channels in any ad8333 are inherently synchronous. however, when multiple ad8333s are used, it is possible that their dividers wake up in different phase states. the function of the rset pin is to phase align all the lo signals in multiple ad8333s. the 4 lo divider of each ad8333 can initiate in one of four possible states: 0, 90, 180, or 270. the internally generated i/q signals of each ad8333 lo are always at a 90 angle relative to each other, but a phase shift can occur during power-up between the internal los of the different ad8333s. the rset pin provides an asynchronous reset of the lo dividers by forcing the internal lo to hang. this mechanism also allows the measurement of nonmixing gain from the rf input to the output. the rising edge of the active high rset pulse can occur at any time, but the duration must be 300 ns minimum (t pw-min ). when the rset pulse transitions from high to low, the lo dividers are reactivated; however, there is a short delay until the divider recovers to a valid state. to guarantee synchronous operation of an array of ad8333s, the 4 lo clock must be disabled when the rset transitions high, and then remain disabled for at least 300 ns after rset transitions low. the timing of the rising edge of rset is not critical as long as the t pw-min is satisfied t hold =holdtime t pw-min = minimum pulse width 4lo rset t pw-min t hold 05543-060 figure 58. timing of the rset signal to 4 lo synchronization of multiple ad8333s can be checked as follows: 1. set the phase code of all ad8333 channels to the same setting, for example, 0000. 2. apply a test signal to a single channel that generates a sine wave in the baseband output, and then measure the output. 3. apply the same test signal to all channels simultaneously, and then measure the output. because all the phase codes of the ad8333s are the same, the combined signal should be n times bigger than the single channel. the combined signal is less than n times one channel if any of the lo phases of individual ad8333s are in error. connecting to the lna of the ad8331/ad8332/ad8334/ad8335 vgas rfxp rfxn +5v ?5v ad8333 ad8332 lna 05543-061 figure 59. connecting the ad8333 to the lna of an ad8332 the rfxx inputs (pin 12, pin 13, pin 28, and pin 29) are optimized for maximum dynamic range when dc-coupled to the differential output pins of the lna of the ad8331/ad8332/ ad8334 or the ad8335 series of vgas and can be connected directly, as shown in figure 59 .
ad8333 rev. d | page 25 of 32 interfacing to other amplifiers if amplifiers other than the ad8332 lna are connected to the input, attention must be paid to their bias and drive levels. for maximum input signal swing, the optimum bias level is 2.5 v, and the rf input must not exceed 5 v to avoid turning on the esd protection circuitry. if ac coupling is used, a bias circuit, such as that illustrated in figure 60 , is recommended. an internal bias network is provided; however, additional external biasing can center the rf input at 2.5 v. ad8333 rfxp rfxn ?5v +5 v 3.74k ? 1.4k ? 1.4k ? 5.23k ? 0.1f 0.1f rf in 05543-062 figure 60. ac coupling the ad8333 rf input to realize the full range of performance, the ad8333 must be driven from a differential source. using a single-ended source is strongly discouraged because of internal supply headroom constraints. lo input the lo input is a high speed, fully differential analog input that responds to differences in the input levels, not in the logic levels. the lo inputs can be driven with a low common-mode voltage amplifier, such as the national semiconductor ds90c401 lvds driver. figure 22 and figure 23 show the range of common-mode voltages and useable lo levels when the lo input is driven with a single-ended sine wave. logic families, such as ttl or cmos, are unsuitable for direct coupling to the lo input. ph11 31 ph10 30 vpos 29 rf1p 28 rf1n 27 vpos 26 enbl 25 i1no 10 9 ph20 11 vpos 12 rf2p 13 rf2n 14 vpos 15 rset 16 i2no 32 ph12 i1po 1 24 ph13 q1po 2 23 comm q1no 3 22 4lop vneg 4 21 4lon comm 5 20 lodc q2no 6 19 ph21 q2po 7 18 ph23 ph22 i2po 8 17 0.1f 0.1f 31.6k ? 33.2k ? 33.2k ? 31.6k ? 0.1f +5v * local oscillator + ? channel 1 + i out channel 2 + q out channel 1 + q out channel 2 + i out 120nh fb ?5v 0.1f +5v v pos 120nh fb 0.1f channel 1 rf in channel 2 rf in channel 1 phase select bits channel 2 phase select bits ? ? + + reset input vpos 0.1f ad8333 * option a l bias network. these components can be deleted if the lo is dc-coupled from an lvds source biased at 1.2v. 05543-040 figure 61. ad8333 basic connections
ad8333 rev. d | page 26 of 32 evaluation board the ad8333-evalz evaluation board provides a platform for test and evaluation of the ad8333 i/q demodulator and phase shifter. the board is shipped fully assembled and tested and is signal ready. a pair of ad8332 low-noise amplifiers (lna) provide input matching and amplification for the differential input of the ad8333. a photograph of the board is shown in figure 62 and a schematic diagram is shown in figure 64 . the board requires dual 5 v supplies capable of supplying 300 ma or greater. except for the optional components shown in grayscale, the board is completely built and tested. 05543-067 figure 62. evaluation board (actual size) features and options the evaluation board has several user-configurable features and options. table 5 lists the configuration switches and their functions. table 5. switch functions switch function configuration enbl enable or disable the ad8333 bottom = disable; top = enable ph10 channel 1 phase bit 0 (lsb) top = 0; bottom = 1 ph11 channel 1 phase bit 1 top = 0; bottom = 1 ph12 channel 1 phase bit 2 top = 0; bottom = 1 ph13 channel 1 phase bit 3 (msb) top = 0; bottom = 1 ph20 channel 2 phase bit 0 (lsb) top = 1; bottom = 0 ph21 channel 2 phase bit 1 top = 1; bottom = 0 ph22 channel 2 phase bit 2 top = 1; bottom = 0 ph23 channel 2 phase bit 3 (msb) top = 1; bottom = 0 rst reset pin left = reset; right = normal phase nibble the phase nibble configures the phase delay for each channel in sixteen 22.5 increments from 0 to 337.5. the increments increase proportionally in a simple binary format from 0h (hexadecimal) to fh. table 4 lists the phase shift and corresponding code for each bit. the bits are labeled 0 and 1, corresponding to low and high, respectively, on the silkscreen. the switches select the desired state. enable and reset switches for normal operation, place a switch in the upper position of enbl. to disable the ad8333, move the switch to the lower position. for normal operation, the switch for rst is in its right position. when the switch is in the left position, the device counter is held in reset and no mixing occurs. fixed options several options can be realized by adding or changing resistors. lna input impedance the shipping configuration of the input impedance of the lna is 50 to match the output impedance of most signal generators. input impedances up to 6 k are obtained by selecting the r9 and r10 values. details concerning this circuit feature are found in the ad8332 data sheet. for reference, table 6 lists common values of input impedance and corresponding feedback resistor values. table 6. lna external componen t values for typical values of source impedance r in () r fb , nearest std 1% value () c sh (pf) 50 280 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k none 6 k none current summing the output transimpedance amplifiers, a1 through a4, are configured as i-to-v converters to convert the output current of the ad8333 to a voltage. the low-pass filters formed by the feedback components are designed for single-channel operation with 5 v supplies. optional resistors r4 and r5 sum the two channels. with r4 and r5 installed, r2 and r3 are removed, and then the sum of the outputs is seen at the i1xo and q1xo output sma connectors. the user has the option to adjust the values of r39, r40, r41, or r42 according to the power supply voltages and expected input current levels. for the same supply voltages, if two channels are summed together, the feedback resistors are halved and the filter capacitor values doubled to optimize the output swing.
ad8333 rev. d | page 27 of 32 filter capacitors c26, c29, c31, and c 32 establish the roll-off characteristic according to the following well-known equation: rc f = 1 where r is the value of r39, r40, r41, or r42, and c is the value of c26, c29, c31, or c32. reset input for normal operation, the reset input is high (no reset). to drive the reset with a dynamic signal, a provision is made to connect a signal generator at the rst input. a 49.9 , 0603 surface-mount resistor can be installed at r15 to terminate the reset input for pulsed experiments. in this configuration, the switch at rst is not used and must be removed to avoid loading the power supply. measurement setup figure 63 is a layout of the ad8333-evalz showing the con- nectors and switches. figure 65 shows a typical board and test equipment setup with two signal generators, a power splitter, and a 5 v, 300 ma (minimum) power supply. for ease in observing waveforms, the signal generators can be synchronized. remember that the f 4lo signal generator frequency is four times that of the nominal frequency of the rf source. for example, to detect signals with a nominal center frequency of 5 mhz, an f 4lo frequency of 20 mhz is applied to the oscillator input. for an applied rf signal of 5.01 mhz, the mix frequencies are 10 khz and 10.01 mhz. because of the low-pass active filter of the transconductance amplifiers (a1 through a4), the 10.01 mhz component is suppressed, and only the 10 khz is observed at the output. take care to avoid overdriving the lna input of the ad8332. the lna gain is 19 db (9.5) and the maximum output swing must not be exceeded; ?10 dbm suffices for many experiments. the f 4lo input is ac-coupled to a 5 v lvds buffer to provide an ideal interface to the ad8333. the f 4lo level is frequency dependent; refer to figure 22 for minimum signal levels, and then adjust the generator output level accordingly. g 0 5543-066 figure 63. evaluation board assembly
ad8333 rev. d | page 28 of 32 evaluation board schematic and artwork comm q2no q1po q1no q2po ph12 4lop p h1 3 vneg i1po 9 1 011 13 14 15 1 6 8 7 6 5 1 4 3 2 19 17 18 24 20 23 22 21 26 25 27 30 29 28 ph22 lodc ph23 4lon co mm ph21 ph20 rf2n vpos vpos i2no rset rf2p i2po vpos vpos rfin 31 rfip ph10 enbl ph11 i1no 32 1 2 c17 0. 1 f c41 0.1f c4 8 0.1 f c 36 0. 1 f c2 4 0.1 f vpos rs t r1 10 0 ? +5 v -5v r13 49.9 ? ph11 ph13 ph10 ph21 ph2 2 ph23 +5v rs t c51 0 .1 f q2 r42 78 7 ? +5vs i2 c52 0.1 f -5vs c3 3 5pf c32 2.2 nf r38 0 ? 27 1 8 3 4 5 6 a4 ad802 1 r41 78 7 ? c5 0 0.1 f -5vs c3 0 5pf c31 2.2 nf r35 0 ? 27 1 8 3 4 5 6 c4 9 0.1 f a3 ad8021 +5 vs i1 r39 78 7 ? c45 0.1f -5v c2 7 5pf c26 2.2 nf r32 0 ? l7 120nhfb 27 1 8 3 4 5 6 c44 0. 1 f l6 120nh fb a1 ad802 1 +5v l4 120nhfb q1 r40 78 7 ? c4 7 0.1 f -5vs c2 8 5pf c29 2.2 nf r33 0 ? 27 1 8 3 4 5 6 c46 0. 1 f a2 ad802 1 +5 vs r22 20 ? r23 20 ? vpo s enbl l3 12 0nh fb lop + - + - + - + - -5vs +5vs c11 0.1 f c4 0.1 f c42 0.1 f vps in2 c4 3 1nf c13 0.1 f c3 22 pf l2 120 nh fb c4 0 .0 18 f r10 274 ? r9 27 4 ? c6 0.1 f l5 120 nh fb 29 303132 28 252627 com1 lop1 vip1 vin1 enbl vcm1 enbv hilo lmd2 lon2 vps 2 inh2 lmd1 lon1 vps 1 inh1 8 7 6 5 1 4 3 2 comm vol2 voh2 v oh1 vol1 nc v psv comm 20 17 18 19 21 22 23 24 1413 91 2 1110 15 16 vip2 vin2 lop2 com 2 rc l m p vcm 2 mode gain c39 . 018 f c1 0.1 f c5 0.1 f in1 l1 12 0 nh fb c2 22 pf vps vps c 14 0.1 f +5vs +5vs +5vs +5 v tp2 tp1 tp4 tp3 z3 ds 90 c4 01 tp8 tp7 tp6 tp5 ph12 4 3 2 5 1 7 6 8 +5v r15 opt r4 op t r5 opt r2 0 ? r3 0 ? c7 10 f 10 v +5 v + -5v c8 10 f 10 v + -5v gnd1 gnd4 gnd3 gnd2 r25 20 ? r26 20 ? r7 1. 5k ? c12 0.1 f r6 3.4 8k ? c9 0. 1 f z 3spa r e vps l ph20 h l h h lh lh lh lh lh lh lh 05543-042 z1 ad8332 dut ad8333 figure 64. evaluation board schematic
ad8333 rev. d | page 29 of 32 05543-065 power supply bottom generator: signal generator for rf input, typical setting: 5.01mhz top generator: signal generator for f 4lo input, typical setting: 20mhz signal 1v p-p power splitter signal input(s) +5v ?5v figure 65. typical board test connections (one channel shown)
ad8333 rev. d | page 30 of 32 board layout the ad8333 evaluation board has four layers. the interconnecting circuitry is located on the outer layers with the inner layers dedicated as power and ground planes. figure 66 , figure 67 , figure 69 , and figure 70 illustrate the copper patterns. 05543-068 figure 66. component side copper 05543-069 figure 67. wiring side copper 05543-072 figure 68. component side silkscreen 05543-070 figure 69. ground plane copper
ad8333 rev. d | page 31 of 32 05543-071 figure 70. power plane copper
ad8333 rev. d | page 32 of 32 outline dimensions compliant to jedec standards mo-220-vhhd-2 011708-a 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indi c ator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 71. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option ad8333acpz-reel ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 ad8333acpz-reel7 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 AD8333ACPZ-WP ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 ad8333-evalz evaluation board 1 z = rohs compliant part. 2 wp = waffle pack. ?2005C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05543-0-9/10(d)

▲Up To Search▲

Price & Availability of AD8333ACPZ-WP

	To Download AD8333ACPZ-WP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .